Language Breakdown
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I-Shaped Developer
I-shapedSpecialist — deep expertise in Verilog
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VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings
This repository is created for conducting RISC-V 5-day workshops
This project has files needed to design and characterise flipflop
PicoRV32 - A Size-Optimized RISC-V CPU
Scripts for 1D- and 2D- NMOS device modelling and simulation
Commit files needed for SPI hierarchical implementation
all material for the VSD-HDP program
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